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ds97key0204 p r e l i m i n a r y 1 1 p reliminary c ustomer p rocurement s pecification z86k13/k14/k15 k16/k17/k18 1 cmos z8 8-b it mcu k eyboard c ontrollers features n 4.5v to 5.5 v operating range n 0 c to +70 c operating temperature range n 188 bytes of ram n low-power consumption: 60 mw @ 5 mhz n five vectored, priority interrupts from five different sources n a programmable 8-bit counter/timer, with 6-bit programmable prescaler n power-on-reset (por) timer, hardware watch-dog timer (wdt) n digital inputs cmos levels with internal pull-up resistors n four direct connect led drive ports n on-chip rc oscillator (z86k13/14/15) n on-chip oscillator that accepts a crystal, ceramic resonator, lc, or external clock drive (z86k16/17/18) n low system emi emission general description the z86kxx keyboard controllers are full-featured mem- bers of the z8 mcu family offering a unique register-to- register architecture that avoids accumulator bottlenecks and is more code efficient than risc processors. for keyboard applications demanding powerful i/o capa- bilities, the z86kxx provides 32 pins dedicated to input and output for row, column, clock, data, and leds. the on-chip counter/timer is available to relieve the system of administering real-time tasks. five different internal or external interrupt sources are maskable and prioritized in which a vectored address is provided for efficient interrupt subroutine handling and multitasking functions. the z86k15 achieves low emi by means of several modi- fications in the output drivers and clock circuitry of the de- vice. rom i/o speed pin count/ device (kb) lines (mhz) package z86k13 2 32 4-5 40-dip, 44-plcc, 44-qfp, cob z86k14 3 32 4-5 40-dip, 44-plcc, 44-qfp, cob z86k15 4 32 4-5 40-dip, 44-plcc, 44-qfp, cob z86k16 2 32 4-5 40-dip, 44-plcc, 44-qfp, cob z86k17 3 32 4-5 40-dip, 44-plcc, 44-qfp, cob z86k18 4 32 4-5 40-dip, 44-plcc, 44-qfp, cob
z86k13/k14/k15/k16/k17/k18 cmos z8?8-bit mcu keyboard controllers zilog 2 p r e l i m i n a r y ds97key0204 general description (continued) notes: all signals with a preceding front slash, ?? are active low. for example, b//w (word is active low); /b/w (byte is active low, only). power connections follow conventional descriptions below: connection circuit device power v cc v dd ground gnd v ss figure 1. z86kxx functional block diagram port 3 interrupt control port 2 i/o (bit programmable) alu flags register pointer machine timing & inst. control program counter gnd xtal1 xtal2 output input port 0 port 1 open-drain output open-drain output wdt por input 4 4 4 8 8 counter/ timers usb sie and trans register file 208 x 8-bytes program memory 4 kb rom vcc d+ d- 3.3 v vr vcc
z86k13/k14/k15/k16/k17/k18 zilog cmos z8?8-bit mcu keyboard controllers ds97key0204 p r e l i m i n a r y 3 1 pin description figure 2. 40-pin dip con?uration p30 p31 p32 p33 *nc *nc p27 p26 p25 p24 gnd vcc p00 p01 p02 p03 p04 p05 p06 p07 p23 p22 p21 p20 p37 p36 p35 p34 rcin/xtal1 agnd/xtal2 gnd vcc p17 p16 p15 p14 p13 p12 p11 p10 40 z86kxx dip 1 20 21 notes: *pin 5 and 6 used for testing ground during normal operation. when pin 5 is connected to v cc . pin 6 is clk out. when pin 5 is connected to gnd, pin 6 outputs nothing. these pins must be tied to ground in application. table 1. 40-pin dip pin identi?ation pin # symbol function direction 1-4 p30-p33 port 3, pins 0,1,2,3 input 5-6 nc tied to gnd 7-10 p27-p24 port 2, pins 7,6,5,4 in/output 11 gnd ground 12 v cc power supply input 13-20 p00-p07 port 0, pins 0,1,2,3,4,5,6,7 output 21-28 p10-p17 port 1, pins 0,1,2,3,4,5,6,7 output 29 v cc power supply 30 gnd ground 31 agnd/xtal2 analog ground or crystal clock out 32 rcin/xtal1 rcin/crystal oscillator clock input 33-36 p34-p37 port 3, pins 4,5,6,7 output 37-40 p20-p23 port 2, pins 0,1,2,3 input
z86k13/k14/k15/k16/k17/k18 cmos z8?8-bit mcu keyboard controllers zilog 4 p r e l i m i n a r y ds97key0204 pin description (continued) figure 3. 44-pin plcc pin assignments z86kxx plcc 7 17 nc p27 p26 p25 p24 gnd vcc p00 p01 p02 p03 nc p36 p35 p34 rcin/xtal1 nc agnd/xtal2 gnd vcc p17 nc p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 nc nc p33 p32 p31 p30 p23 p22 p21 p20 p37 1 28 18 40 39 29 6 notes: pins 5 and 6 used for testing. ground during normal operation when pin 43 is connected to v cc , pin 44 is clkout. when pin 43 is connected to gnd. pin 44 outputs nothing. table 2. 44-pin plcc pin assignments pin # symbol function direction 1-4 p30-p33 port 3, pins 0,1,2,3 input 5-7 nc test pins (gnd) 8-11 p27-p24 port 2, pins 4,5,6,7 in/output 12 gnd ground 13 v cc power supply 14-21 p00-p07 port 0, pins 0,1,2,3,4,5,6,7 output 22-28 p10-p16 port 1, pins 0,1,2,3,4,5,6 output 29 nc not connected 30 p17 port 1, pin 7 output 31 v cc power supply 32 gnd ground 33 agnd/ xtal2 analog ground or crystal clock out 34 nc not connected 35 rcin/ xtal1 rcin/crystal oscillator clock input 36-38 p34-p37 port 3, pins 4,5,6,7 output 39 nc not connected 40 p37 port 3, pin 7 output 41-44 p20-p23 port 2, pins 0,1,2,3 in/output table 2. 44-pin plcc pin assignments pin # symbol function direction
z86k13/k14/k15/k16/k17/k18 zilog cmos z8?8-bit mcu keyboard controllers ds97key0204 p r e l i m i n a r y 5 1 figure 4. 44-pin qfp pin assignments 34 44 p37 p20 p21 p22 p23 p30 p31 p32 p33 nc nc p16 p15 p14 p13 p12 p11 p10 p07 p06 p05 p04 nc p27 p26 p25 p24 gnd vcc p00 p01 p02 p03 nc p36 p35 p34 rcin/xtal1 nc agnd/xtal2 gnd vcc p17 nc 1 23 33 z86kxx qfp 11 22 12 notes: pins 43 and 44 are used for testing ground during normal operation. when pin 45 is connected to v cc , pin 46 is clkout. when pin 45 is connected to gnd. pin 46 outputs nothing. table 3. 44-pin qfp pin identification pin # symbol function direction 1 nc not connected 2-5 p24-p27 port 2, pins 4,5,6,7 in/output 6 gnd ground 7v cc supply voltage 8-15 p00-p07 port 0, pins 0,1,2,3,4,5,6,7, output 16-22 p10-p16 port 1, pins 0,1,2,3,4,5,6 output 23 nc not connected 24 p17 port 1, pin 7 output 25 v cc supply voltage 26 gnd ground 27 agnd/ xtal2 analog ground/ crystal clock out 28 nc not connected 29 rcin / xtal1 rcin/crystal oscillator clock input 30-32 p34-p36 port 3, pins 4,5,6 output 33 nc not connected 34 p37 port 3, pin 7 output 35-38 p20-p23 port 2, pins 0,1,2,3 input 39-42 p30-p33 port 3, pins 0,1,2,3 input 43-44 nc test pins (gnd) table 3. 44-pin qfp pin identification pin # symbol function direction
z86k13/k14/k15/k16/k17/k18 cmos z8?8-bit mcu keyboard controllers zilog 6 p r e l i m i n a r y ds97key0204 absolute maximum ratings stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only; operation of the device at any condition above those indicated in the operational sec- tions of these specifications is not implied. exposure to ab- solute maximum rating conditions for extended periods may affect device reliability. standard test conditions the characteristics listed here apply for standard test con- ditions as noted. all voltages are referenced to gnd. pos- itive current flows into the referenced pin (figure 5). capacitance t a = 25 c; v cc = gnd = 0v; f = 1.0 mhz; unmeasured pins returned to gnd. frequency tolerance 10% symbol description min max units v cc supply voltage* ?.3 +7.0 v t stg storage temp ?5 +150 c t a oper ambient temp 0 +105 c note: * voltage on all pins with respect to gnd. figure 5. test load diagram from output under test 150 pf parameter max input capacitance 12 pf output capacitance 12 pf i/o capacitance 12 pf
z86k13/k14/k15/k16/k17/k18 zilog cmos z8?8-bit mcu keyboard controllers ds97key0204 p r e l i m i n a r y 7 1 dc characteristics v cc = 5.0v 10% @ 0 c to +70 c sym parameter min max typ* unit condition v ch clock input high voltage 0.7 v cc v cc + 0.3v 2.5 v driven by external clock generator v cl clock input low voltage gnd ?.3 0.2 v cc 1.5 v driven by external clock generator v ih input high voltage 0.7 v cc v cc + 0.3 2.5 v v il input low voltage gnd ?.3 0.2 v cc 1.5 v v oh output high voltage v cc ?.4 4.7 v i oh = ?.0 ma v oh output high voltage v cc ?.6 v i oh = ?.0 ma (see note 1 below.) v ol output low voltage .4 v i ol = 4 ma v ol output low voltage .8 v i ol = 4 ma (see note 1 below.) i ol output low 10 20 ma v ol = v cc ?.2 v (see note 1, 2 below.) i ol output leakage ? 1 <1 m av in = 0v, 5.25v i cc v cc supply current 12 6 ma @ 5.0 mhz i cc1 halt mode current 2 ma @ 5.0 mhz i cc2 stop mode current 10 m a r p pull up resistor 6.76 14.04 10.4 k ohm r p pull up resistor (p26-p27) 1.8 3 2.4 k ohm notes: * typical @ 25 c 1. ports p37-p34. these may be used for leds or as general-purpose outputs requiring high sink current. 2. v cc = 5.0v 5% @ 0 c to + 70 c
z86k13/k14/k15/k16/k17/k18 cmos z8?8-bit mcu keyboard controllers zilog 8 p r e l i m i n a r y ds97key0204 ac electrical characteristics t a = 0 c to 70 c v cc 5 mhz no symbol parameter note[4] min max units notes 1 tpc input clock period 5.0v 200 250 ns 1 2 trc,tfc clock input rise & fall times 5.0v 25 ns 1 3 twc input clock width 5.0v 37 ns 1 4 twtinl timer input low width 5.0v 70 ns 1 5 twtinh timer input high width 5.0v 2.5tpc 1 6 tptin timer input period 5.0v 4tpc 1 7 trtin, timer input rise & fall timer 5.0v 100 ns 8a twil int. request low time 5.0v 70 ns 1,2 8b twil int. request low time 5.0v 3tpc 1,3 9 twih int. request input high time 5.0v 3tpc 1,2 10 twsm stop mode recovery width spec 5.0v 5tpc ns 11 tost oscillator start-up time 5.0v 5tpc 12 twdt watch-dog timer delay time 5.0v 53 ms 13 t por power--on reset 5.0v 106 130 ms notes: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request through port 3 (p31-p33). 3. interrupt request through port 3 (p30). figure 6. additional timing clock 1 3 4 8 2 2 3 tin irqn 6 5 7 7 11 cl oc k setup 10 9 stop mode recover y sourc e
z86k13/k14/k15/k16/k17/k18 zilog cmos z8?8-bit mcu keyboard controllers ds97key0204 p r e l i m i n a r y 9 1 pin functions rcin. a precision resistor is connected between this pin and the power supply to form the precision rc oscillator. clkout. this pin is the system clock of the z8 and runs at the frequency of the rc oscillator (test only). port 0 (p07-p00). port 0 is an 8-bit, cmos-compatible open-drain output (figure 7). figure 7. port 0 configuration port 0 (open-drain output) z86kxx 8 pad output
z86k13/k14/k15/k16/k17/k18 cmos z8?8-bit mcu keyboard controllers zilog 10 p r e l i m i n a r y ds97key0204 port 1 (p17-p10). port 1 is an 8-bit cmos compatible open-drain output port (figure 8). figure 8. port 1 configuration port 1 open-drain output z86kxx pad output 8
z86k13/k14/k15/k16/k17/k18 zilog cmos z8?8-bit mcu keyboard controllers ds97key0204 p r e l i m i n a r y 11 1 port 2 (p27-p20). port 2 is an 8-bit cmos compatible port with 4-bit input, 4-bit programmable i/o (figure 9). p20- p25 have 10.4k ( 35%) pull-up resistors. p26-p27 have 2.4k ( 25%) pull-up resistors. figure 9. port 2 configuration open-drain out oen in pad 2.4k input (c) ports p26-p27 open-drain out oen in pad input (b) ports p24-p25 10.4 kohm pad 10.4 k input z86kxx input i/o 4 (a) ports p20-p23 vcc vcc vcc
z86k13/k14/k15/k16/k17/k18 cmos z8?8-bit mcu keyboard controllers zilog 12 p r e l i m i n a r y ds97key0204 pin functions (continued) port 3 (p37-p30). port 3 is an 8-bit, cmos-compatible four-fixed input (p33-p30) and four-fixed output (p37-p34) i/o port. port 3 inputs have 10.4 kohm pull-up resistors. outputs are capable of directly driving led. port 3 is configured under software control to provide four external interrupt request signals (irq0-irq3). figure 10. port 3 configuration port 3 z86kxx output pad (a) port 3 p34-p37 (b) port 3 p30-p33 input pad 10.4 kohms
z86k13/k14/k15/k16/k17/k18 zilog cmos z8?8-bit mcu keyboard controllers ds97key0204 p r e l i m i n a r y 13 1 program memory. the 16-bit program counter addresses 4 kb of program memory space at internal locations (fig- ure 11). the first 12 bytes of program memory are reserved for the interrupt vectors. these locations have six 16-bit vectors that correspond to the five available interrupts. byte 12 to byte 4095* consists of on-chip, mask pro- grammed rom. addresses 4096* and greater are re- served. (*2048 for k13/k16, 3072 for k14/k17) register file . the register file (figure 13) consists of four i/o port registers, 188 general-purpose registers (exclud- ing p00-p03), and 11 control and status registers (r3-r0, r191-r4, and r255-r240, respectively). the instructions can access registers directly or indirectly through an 8-bit address field. this allows short, 4-bit register addressing using the register pointer. in the 4-bit mode, the register file is divided into nine working-register groups, each occu- pying 16 continuous locations. the register pointer ad- dresses the starting location of the active working-register group. figure 11. program memory map figure 12. register pointer register 12 11 10 9 8 7 6 5 4 3 2 1 0 on-chip rom location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) reserved irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 reserved 65535 2048/3072/4096 2047/3071/4095 reserved d7 d6 d5 d4 d3 d2 d1 d0 r253 rp reserved working register group default setting after reset = 00000000 figure 13. register file con?uration stack pointer (bits 7-0) r25 5 reserved register pointer program control flags interrupt mask register interrupt request register interrupt priority register reserved port 3 mode port 2 mode t0 prescaler timer/counter0 reserved reserved timer mode reserved not implemented general-purpose registers port 3 port 2 port 1 port 0 r25 4 r253 r252 r251 r250 r249 r248 r247 r246 r245 r244 r243 r242 r241 r240 r 191 r3 r2 r1 r0 spl rp flags imr irq ipr p3m p2m preq t0 tmr p3 p2 p1 p0 r4 location identifiers note:* will not be reset with a stop mode recovery.
z86k13/k14/k15/k16/k17/k18 cmos z8?8-bit mcu keyboard controllers zilog 14 p r e l i m i n a r y ds97key0204 pin functions (continued) figure 14. register file architecture 7 6543210 working register group pointer reserved register %ff %fo %0f %00 z8 reg. file register pointer % ff % fe % fd % fc % fb % fa % f9 % f8 % f7 % f6 % f5 % f4 % f3 % f2 % f1 % f0 spl reserved rp flags imr irq ipr reserved p3m p2m pre0 t0 reserved reserved tmr port registers reg. group (0) register z8 standard control registers % (0) 03 p3 % (0) 02 p2 % (0) 01 p1 % (0) 00 p0 * * reserved note: * will not be reset with a stop mode recovery not available %bf
z86k13/k14/k15/k16/k17/k18 zilog cmos z8?8-bit mcu keyboard controllers ds97key0204 p r e l i m i n a r y 15 1 counter/timers. there is an 8-bit programmable counter/timer (t0) driven by its own 6-bit programmable prescaler (figure 15). the 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. the pres- caler drives its counter, which decrements the value (1 to 256) on the prescaler overflow. when both the counter and prescaler reach the end of count, a timer interrupt request, irq4, is generated. the counter can be programmed to start, stop, restart to continue, or restart from the initial value. the counter can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode) the counter, but not the prescaler, is read at any time without disturbing its value or count mode. figure 15. counter/timers block diagram pre0 initial value register t0 initial value register t0 current value register 6-bit down counter 8-bit down counter ? 4 irq4 write write read internal data bus osc
z86k13/k14/k15/k16/k17/k18 cmos z8?8-bit mcu keyboard controllers zilog 16 p r e l i m i n a r y ds97key0204 pin functions (continued) interrupts. the z86k15 has five different interrupts from five different sources. these interrupts are maskable and prioritized (figure 16). the five sources are divided as fol- lows: four sources are claimed by port 3 lines p33-p30, and the other is claimed by the counter/timer. the interrupt masked register globally or individually enables or dis- ables the five interrupts requests. when more than one interrupt is pending, priorities are re- solved by a programmable priority encoder that is con- trolled by the interrupt priority register. all interrupts are vectored through locations in the program memory. when an interrupt machine cycle is activated an interrupt request is granted. thus, this disables all of the subsequent inter- rupts, saves the program counter and status flags, and then branches to the program memory vector location re- served for that interrupt. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt request needs service. rc oscillator. the z86k13/14/15 provides an internal ca- pacitor to accommodate an rc oscillator configuration. a 1% precision resistor is necessary to achieve 10% accu- rate frequency oscillation. the z86k15 also accepts external clock from (rcin) with (agnd) connected to v cc (figure 17). figure 16. interrupt block diagram irq imr priority logic global interrupt enable vector select interrupt request 5 irq0-irq4 5 ipr figure 17. rc oscillator configuration rcin nc 1% precision clkout vcc rc oscillator external clock rcin agnd vcc
z86k13/k14/k15/k16/k17/k18 zilog cmos z8?8-bit mcu keyboard controllers ds97key0204 p r e l i m i n a r y 17 1 watch-dog timer. the watch-dog timer is activated au- tomatically by power-on if it is enabled in the mask option. the wdt is a retriggerable one-shot timer that resets the z8 if it reaches its terminal count. the wdt is driven by the system clock. it must be refreshed at least once during each time cycle by executing the wdt instruction. wdt can be enabled by mask option. (figure 18) wdt hot bit. bit 7 of the interrupt request register (irq register fah) determines whether a hot start or cold start occurred. a cold start is defined as reset occurring from power-up of the z86k15 (the default upon power-up is 0). a hot start occurs when a wdt time-out has occurred (bit 7 is set to 1). bit 7 of the irq register is read-only and is automatically reset to 0 when read. watch-dog timer . the wdt time-out is . wdt during halt (d5-r250). this bit determines wheth- er or not the wdt is active during halt mode. the default is 1, and a 1 indicates active during halt. 294912ms fhz () ---------------------------- figure 18. wdt turn-on timing after reset vcc internal reset por reset delay * reset delay = por 147 ms 10% at 4 mhz. 18 tpc
z86k13/k14/k15/k16/k17/k18 cmos z8?8-bit mcu keyboard controllers zilog 18 p r e l i m i n a r y ds97key0204 pin functions (continued) power-on-reset (por). a timer circuit is triggered by the system oscillator and is used for the power-on reset (por) timer function. the por time allows v cc and the os- cillator circuit to stabilize before instruction execution be- gins. por period is defined as: the por timer circuit is a one-shot timer triggered by one of two conditions: 1. power fail to power ok status 2. stop-mode recovery the por time is a nominal 147 ms 10%. at 4 mhz the por timer is bypassed after stop-mode recovery. halt. halt turns off the internal cpu clock, but not the rc oscillator. the counter/timer and external interrupts irq0, irq1, irq2, and irq3 remain active. the z86k15 is recovered by interrupts, either externally or internally (figure 19). stop. this instruction turns off the internal clock and os- cillator. it reduces the standby current to less than 10 m a. the stop mode is terminated by a reset only or external reset. this causes the processor to restart the application program at address 000c (hex) or the active external in- terrupt vector. in order to enter stop (or halt) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. to do this, the user must execute a nop (opcode=ffh) immediately be- fore the appropriate sleep instruction, such as: the bit 6 of irq registers are flags for stop mode re- covery (figure 20). cold or warm start (d6). this bit is set upon entering stop mode. a 0 (cold) indicates that the device is awak- ened by a por/wdt reset. a 1 (warm) indicates that the device is awakened by a smr source. this bit is reset when read. negative transition on any of the designated row input pins or host data line will recover z86kxx from stop mode. por (ms) = 589824 f (hz) ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode figure 19. irq register d7 d6 d5 d4 d3 d2 d1 d0 r250 irq irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = p30 input irq4 = to wdt during halt 0 off * 1 on stop flag 0 por/wdt* 1 stop recovery * on reset wdt hot bit (read only) 0 por* 1 wdt timeout figure 20. stop-mode recovery source to internal reset p20-p26, p30-p33
z86k13/k14/k15/k16/k17/k18 zilog cmos z8?8-bit mcu keyboard controllers ds97key0204 p r e l i m i n a r y 19 1 z8 control register diagrams figure 21. timer mode register (f1 h : read/write) counter/timer 0 register figure 22. (f4 h : read/write) prescaler 0 register figure 23. (f5 h : write only) d7 d6 d5 d4 d3 d2 d1 d0 0 = disable t0 count 1 = enable t0 count 0 = no function 1 = load t0 r241 tmr reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 t0 initial value (when write) (range: 1-256 decimal 01-00 hex) t0 current value (when read) r244 t0 d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 0 = t single pass 1 = t modulo n 0 reserved (must be 0) prescaler modulo (range: 1-64 decimal 01-00 hex) r245 pre0 port 2 mode register figure 24. (f6 h : write only) port 2 open drain mode register figure 25. (f7 h : write only) figure 26. interrupt priority register (f9 h : write only) d7 d6 d5 d4 d3 d2 d1 d0 p24-p27 i/o definition 0 defines bit as outpu t 1 defines bit as input r246 p2m reserved d7 d6 d5 d4 d3 d2 d1 d0 0 port (24-27) open-drain 1 port (24-27) push-pull reserved (must be 0) r247 p3m d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority reserved = 000 c > a > b = 001 a > b > c = 010 a > c > b = 011 b > c > a = 100 c > b > a = 101 b > a > c = 110 reserved = 111 reserved irq0, irq2 priority (group b) 0 = irq2 > irq0 1 = irq0 > irq2 irq1, irq4 priority (group c) 0 = irq1 > irq4 1 = irq4 > irq1 reserved (must be 0) r249 ipr
z86k13/k14/k15/k16/k17/k18 cmos z8?8-bit mcu keyboard controllers zilog 20 p r e l i m i n a r y ds97key0204 figure 27. interrupt request register (fa h : read/write) figure 28. interrupt mask register (fb h : read/write) d7 d6 d5 d4 d3 d2 d1 d0 r250 irq irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = p30 input irq4 = to stop delay 0 off * 1 on stop flag 0 por/wdt* 1 stop recovery * on reset wdt hot bit (read only) 0 por* 1 wdt timeout d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) 1 enables irq0-irq4 (d0= irq0) 1 enables interrupts r251 imr figure 29. flag register (fc h : read/write) register pointer figure 30. (fd h : read/write) stack pointer figure 31. (ff h : read/write) d7 d6 d5 d4 d3 d2 d1 d0 user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag r252 flags d7 d6 d5 d4 d3 d2 d1 d0 working registers r4 r253 rp r5 r6 r7 register pointer d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp0-sp7) r255 spl
z86k13/k14/k15/k16/k17/k18 zilog cmos z8?8-bit mcu keyboard controllers ds97key0204 p r e l i m i n a r y 21 1 package information figure 32. 40-pin dip package diagram figure 33. 44-pin plcc package diagram
z86k13/k14/k15/k16/k17/k18 cmos z8?8-bit mcu keyboard controllers zilog 22 p r e l i m i n a r y ds97key0204 figure 34. 44-pin qfp package diagram
z86k13/k14/k15/k16/k17/k18 zilog cmos z8?8-bit mcu keyboard controllers ds97key0204 p r e l i m i n a r y 23 1 ordering information for fast results, contact your local zilog sales office for assistance in ordering the part desired. codes package p = plastic dip v = plastic leaded chip carrier f = quad flat pack speed 05 = 5 mhz environmental c = plastic standard temperature s = 0 c to +70 c ?1997 by zilog, inc. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of zilog, inc. the information in this document is subject to change without notice. devices sold by zilog, inc. are covered by warranty and patent indemnification provisions appearing in zilog, inc. terms and conditions of sale only. zilog, inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. zilog, inc. makes no warranty of merchantability or fitness for any purpose. zilog, inc. shall not be responsible for any errors that may appear in this document. zilog, inc. makes no commitment to update or keep current the information contained in this document. zilog? products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and zilog prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. zilog, inc. 210 east hacienda ave. campbell, ca 95008-6600 telephone (408) 370-8000 fax 408 370-8056 internet: http://www.zilog.com 5 mhz 5 mhz 5 mhz 40-pin dip 44-pin plcc 44-pin qfp z86kxx05psc z86kxx05vsc z86kxx05fsc example : z 86k15 05 p s c is a z86k15, 05 mhz, dip, 0 to +70 c, plastic standard flow environmental flow temperature package speed product number zilog pre?
z86k13/k14/k15/k16/k17/k18 cmos z8?8-bit mcu keyboard controllers zilog 24 p r e l i m i n a r y ds97key0204

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